SUBJECT NAME: VLSI DESIGN. SUBJECT CODE: EC UNIT I CMOS TECHNOLOGY. PART –A (2 MARKS). 1. What are four generations of Integration. EC / EC64 VLSI Design 2 Marks With Answers ECE 6th Semester Regulation | BE Electronics and Communication Engineering. Sixth Semester. 2 MARK QUESTION AND ANSWERS. ECVLSI DESIGN is CMOS technology? Complementary Metal Oxide Semiconductor (CMOS)in which.
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Log In Sign Up. The threshold voltage of a MOSFET is usually defined as the gate voltage where an inversion layer forms the interface between the insulating layer oxide and the substrate body of the transistor. What is enhancement mode FET? A type of FET in which there are no charge carriers present in the channel, when the gate voltage is in zero. In these devices, the increasing the gate voltage will increases the current flow from source to drain.
Drain source on resistance Rds 4. Zero gate voltage drain current Idss 6. Input capacitance Ci 4. What are the steps performed to achieve lithography friendly design?
Checking the layout confirming the design rules spacing, trace width, shorts. Check for the less congested answerz and increasing the spacing of the nets. State different types of oxidation.
Give the major advantages of IC. Size is less 2. What are different generations of integration circuits? Give the variety of integrated circuits ICs. Systems on Chips SOC. What are the various silicon wafer preparations? Crystal growth and doping 2. Ingot trimming and grinding 3. Wafer polishing and etching 5.
What are the different terminals in MOS transistors? What is depletion mode operation MOS? If the channel is initially doped lightly with p type impurity a conducting channel exists at zero gate voltage and the device is said to operate in depletion mode. What is enhancement mode operation of MOS? If the gate field must induce a channel before current can flow and the gate voltage enhances the channel current and such a device is said to the enhancement mode MOS.
State the different types of CMOS processes. Silicon on insulator process 4. What are the steps involved in twin tub process? Thin oxide construction 3. Source and drain implantation 4. Contact cut definition 5.
What is latch up? Latch up is a condition in which the parasitic components give rise to the establishment of low resistance conducting paths between VDD and VSS with disastrous results. Careful control during fabrication is necessary to avoid this problem. What is stick diagram?
EC VLSI DESIGN Important Part A 2 Mark Part B 16 Mark Question Bank
It is used to convey information through the use of color code. Also it is the cartoon of a chip layout. What are the uses markss stick diagram? It can be drawn much easier and faster than a complex layout.
These are especially important tools for layout built from large cells. Give the various color coding used in stick diagram. What are the advantages of silicon on insulator SOI process? No latch up 2. Due to absence of bulks transistor structures are denser than bulk silicon. State the advantages of CMOS process. Low power dissipation 2. High packing density 3. Low input impedance 5. Low delay sensitivity to load. What are short clsi devices?
Transistors with channel length less than 3 5 microns are termed as short channel devices. With short channel devices the ratio between the lateral and mwrks dimensions are reduced. State the different operating regions for an MOS transistor. Cut off region 2. Non saturated region 3. Define threshold voltage of CMOS. The threshold voltage, Vt for a MOS transistor can be defined as the voltage applied between the gate and the source of the MOS transistor below which the drain to source current, IDS effectively e2354 to zero.
What is body effect? The threshold voltage VT is not a constant with respect to the voltage difference between the substrate and the source of MOS transistor. This effect is called substrate bias effect or body effect. What is channel length modulation? The current between drain and source terminals is constant and independent of the applied voltage over the terminals. The effective length of the conductive channel is actually modulated by the applied voltage VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the effective channel.
Differentiate between channeled and channel less gate array. Channels gate array Channel less gate array Only the interconnect is 1. Only the top few mask layer customized customized. The interconnect uses No predefined areas are set aside between 2. Logic density is less Logic density is higher N channel transistors have greater switching speed when compared to PMOS transistors. Draw the basic CMOS inverter circuit.
What is a pull down device?
A device connected marrks as to pull the output voltage to the lower supply voltage usually 0 V is called pull down device. What is pull up device? A device connected so as to pull the output voltage to the upper supply voltage usually VDD is called pull up device. Give the different symbols for transmission gate.
What is mean by power and power dissipation? Power is the rate at which energy is delivered or exchanged; power dissipation is the rate at which energy is taken from the source VDD and converted into heat electrical energy is converted into heat energy during operation. What is mean by PDP?
What are two types of power dissipation? Define elmore delay model. It is an analytical method used to estimate the RC delay in a network. Elmore delay model estimates the delay of a RC ladder as the sum over each node in the ladder of the resistance Rn 1 between that node and a supply multiplied by the capacitor on the nodes.
What are the general properties of elmore delay model? What is static power dissipation? The power dissipation due to leakage current when the MOS transistor is in idle state is called the static power dissipation.
Static power due to Sub threshold conduction through OFF transistors Tunneling current through gate oxide Leakage through reverse biased diodes Contention current in radioed circuits. What is dynamic power dissipation? Power dissipation is due to circuit switching to charge and discharge the output load capacitance at a particular node at operating frequency is called dynamic power dissipation.
What are the methods available to reduce dynamic power dissipation? Reducing the product of capacitance and its switching frequency. Eliminate logic switching that is not necessary for computation.
Reduce activity vlei Reduce supply voltage What are the methods to reduce static power dissipation? By selecting multi threshold voltages on circuit paths with low Vt transistors while leakage on other paths with high Vt transistors.
By using two operating modes, active and standby for each function blocks. By adjusting the body bias i. By using sleep transistors to isolate the supply from the block to achieve significant leakage power savings.